There is wide agreement that one of the most important impediments to the performance of current and future pipelined superscalar processors is the presence of conditional branches in the instruction stream. Accurate branch prediction is required to overcome this performance limitation. Many branch predictors have been proposed to help to alleviate this problem, including the Two-Level Adaptive Branch Predictor, and more recently, hybrid branch predictor.
In a less idealized environment, such as a time-sharing system, code of interest involves context switches. Context switches, even at fairly large intervals, can seriously degrade the performance of many of the most accurate branch prediction schemes. Branches in different address spaces are aliased and aliasing among different address spaces' branches make the prediction accuracy degrade. In this study, we measure the effect of context switch on the branch prediction accuracy in various situation and show the feasibility of our new mechanism which save and restore branch predictor table at every context switch.
