We have studied defect creation in hydrogenated amorphous silicon thin film transistors by measuring the current-voltage characteristic curves with the bias condition varied. It is found that there is a distortion in the current -voltage curves after a spatially asymmetric bias-stress.
Comparing the threshold voltages estimated by the typical method in both the saturation regime and the linear regime, we find very different values for each cases by superlinearity of current-voltage curve, where the values of threshold voltage vary according to the positions of extrapolation. However, estimations based on our modified model yield ensuring good consistency with respect to the extraction method of threshold voltage in the two regimes.
And then, in order to explain the unusual behavior in the current-voltage characteristic curves due to the spatially asymmetric positive gate bias of the gate-source voltage and gate-drain voltage, we employed increased defects at the lower part of the gap which have an asymmetric distribution along the channel. To fit our experimental data, for simplicity, we use the increased density of states of defects in the lower part of the gap multiplied by factors of 2, 5 and 20 for 340, 350 and 383 K, respectively, in the source region and the density of states of annealed states in the drain region. Good agreement is obtained.
