In recent trends, there are emerging markets of DSPs and customer electronics which require high computing capabilities. Multiplication circuits are the most important part of such systems because they consume much of the are and the data bit width gets widen. As well, the speed and the power of multipliers are the critical factors of chip design.
As the data bit width gets widen, it is the partial product generator which influences the performance of the multiplier, mostly. Therefore it is necessary to analyze the multiplier with the ratio of the performance versus the data bit width. In this thesis, the performance of modified booth multiplier is measured by the ratio. The results show that the ratio is rapidly dropped in the 64 x 64 bit multiplication and the compensation of the performance must be done in the multiplier with wide data bit width. Modular array multiplier is introduced to maintain the ratio in any data bit width and to be adopted to high speed synthesizer.