A hybrid clock recovery circuit composed of an analog phase-locked loop(APLL) and digital blocks for a 100BaseT4 ethernet transceiver is described. This circuit operates at a data rate of 25MHz from a single 5V power supply and achieves fast aquisition in the preamble period. The total power dissipation is about 45mW and the active area is 1000㎛×800㎛$(1240mkl^2)$ in a 0.6㎛ single-poly double-metal n-well CMOS process. This hybrid clock recovery circuit is applicable to the on-chip design where several clock recovery circuits are needed.
