ATM Switches are key blocks for ATM network. They need internal queuing, because of output contention. This paper describes issues in the design of a memory system for ATM switch. The key to the switch's operation is a 3 queue address handling and a pipelined memory structure.
In addition to Anderson's paper, 3 queue address handling method that design methodology for variable length queue give more good cell loss probability under burst traffic without additional expanse. And also, pipelined memory structure improves matching probability under PIM algorithm.
This paper present a organization for a 3 queue address handling method and a pipelined memory structure under PIM cell scheduling algorithm. The memory consists of SRAM.
C-code simulation show that 3 queue address handling method improves the cell loss probability. Afterwards, this memory system is implemented by Verilog HDL and simulated by Verilog- XL. Also, HSPICE simulated.
