The discrete cosine transform(DCT) is considered to be the most effective method in image data compression and has been commonly adopted as a key technique in the various international standards for image compression.
In this thesis, a low-power ROM shared DCT/IDCT processor is designed. A new ROM shared DCT/IDCT architecture to utilize Chen’s fast algorithm and distributed arithmetic is proposed. The proposed architecture reduces the number of ROM’s by 63%, adders by 19%, and pipeline registers by 30%. A new carry-select adder in which section adder is implemented with carry-lookahead adder and carry generation logic is minimized by resource sharing is designed. As a result, the number of gates is reduced by 20%. To reduce power consumption, gated latch is used instead of shift register which dissipates a lot of power. Totally, the processor designed in this thesis reduces the number of gates by about 25%.
The proposed architecture is verified by C-code simulations. The processor is designed with 5V power supply, 0.6㎛ triple-metal standard cell library. The processor is estimated to have 120MHz clock frequency and 11.76㎟ core area.
