This thesis presents a CMOS IF-IC(Intermediate Frequency Integrated Circuit) for GPS(Global Positioning System) data receivers. The proposed GPS IF-IC consists of 280MHz PLL(Phase-Locked Loop), AGC(Automatic Gain Control) loop, on-chip active MOSFET-C filter and 2-bit A/D converter. In the proposed IF-IC, a 35.42MHz input signal from GPS RF part is mixed with a 31.11MHz LO(Local Oscillator) signal generated by PLL. Subsequently, the output of the mixer goes through an $6^{th}$ order active MOSFET-C bandpass filter having a center frequency of 4.3MHz and a band of about 3.5MHz to remove harmonic frequency components. The output of the filter is digitized to 2-bit signals of magnitude and sign for digital signal processing part. Hspice circuit simulation is performed to overall circuits with the model parameters of MOSIS 1.2μm double-poly double-metal process. The results show that the proposed CMOS GPS IF-IC operates well with moderate power consumption of 40mW at 5V and AGC range over 60dB.
