A novel noise model of GaAs MESFETs is proposed, which is verified using MESFETs with different structures. Previously reported noise models of MESFETs are analyzed using both measured data and the equations derived in this work. As a result, it is verified that only two independent white noise sources of intrinsic MESFET is sufficient to describe the noise characteristics of a GaAs MESFET as a function of frequency. One of the noise sources is the voltage noise source placed in series with an intrinsic resistor at gate port and the other is the current noise source placed in parallel with a voltage-controlled current source at drain port. Noise data extracted from a GaAs MESFET fabricated by ion implantation process are used to examine all sets of frequency-independent noise parameters previously reported. There are no complete set which is applicable to estimate the dependence of noise characteristics on bias level. The purpose of this work is find the set of frequency-independent noise parameters which can be simply expressed with bias level.
A new set of two frequency-independent noise parameters which are linearly dependent on bias level is used for the noise model of this work. One is noise temperature of intrinsic resistor and the other is equivalent noise conductance. Noise temperature of intrinsic resistor is used to represent the magnitude of the voltage noise source placed at gate port and equivalent noise conductance is used for the current noise source placed at drain port. These two frequency-independent noise parameter have a linear dependence on bias level. This make it possible to describe the dependence of frequency-independent noise parameters on bias level with four parameters which are independent of bias level as well as frequency. MESFETs fabricated on epitaxial grown GaAs wafers are also used for verifying the noise model proposed in this work. The model proposed in this work agrees well with the measured data. This suggests that the model can be applied to GaAs MESFETs with different doping structures.
The model in this work is examined in designing a two-stage low noise amplifier MMIC. An optimum gate width and a bias level of the first stage MESFET are determined using the noise model. The MMIC fabricated using ion-implantation process shows good performance of noise figure of 1.5 dB, which is coincident with the designed one.
It is demonstrated that the noise model can be useful for designing a low noise amplifier MMICs as well as for predicting the noise parameters of GaAs MESFETs.
