Energy efficiency has become one of the most important concerns in VLSI design. In this paper, a new type of logic circuit, called Charge Recycling Differential Logic (CRDL), has been proposed to meet the requirement of low-power electronic devices. CRDL improves power efficiency by utilizing a charge recycling technique, while keeping the speed comparable to that of conventional dynamic circuit techniques. Besides the power-efficient operation, this logic family has several interesting advantages. Firstly, CRDL is inherently a static logic although the operation of this circuit is based on precharging action like the conventional dynamic logic circuits. Thus, it has an improved noise margin, and eliminates problems due to the existence of dynamic nodes. In addition, the operation of CRDL causes less di/dt noise on the supply lines as compared with that of the conventional precharge schemes, since it uses internally stored charges for operations instead of drawing them from outside.
Synchronous and asynchronous pipeline configurations with CRDL are also introduced with a set of additional advantages over conventional pipeline structures. First of all, when a true single-phase-clock latch (TSPC) is connected to the output of a CRDL circuit, an inherent noise margin problem due to the internal dynamic node in the TSPC latch is eliminated without any additional device. Two static latches, newly proposed in this paper to be used with the proposed logic circuit, have a better performance than the conventional transmission gate latch. Moreover, a synchronous pipeline configuration implemented using CRDL with novel latches is shown to be safely operated by a single-phase clocking scheme. The timing analysis of this configuration for reliable operations has also been addressed. An asynchronous pipeline configuration with CRDL eliminates the need for completion detectors which are usually attached at the output of a function block in conventional configurations, further improving the power-efficiency. The standard Muller C-element has been modified to confirm delay-insensitive operations with half-swing signal applied to the input of the C-element.
A preliminary version of the 8-bit Manchester carry chain was fabricated using a 0.8 ㎛ single-poly double-metal n-well CMOS technology to verify the relative performance of the proposed logic family. The measurement result indicates that about 27% improvement in power-delay product is obtained compared with DCVS (Differential Cascode Voltage Switch) logic in good agreement with the simulation result. In addition, simulation results for an improved version of the carry chain and full adder with extracted parasitic from the layout, which are now being fabricated, show that the improvements are by as much as 54% and 20%, respectively. From the above experimental and simulation results including the simulation for a 32-bit adder, and a 16-bit fully asynchronous Booth multiplier, which were designed to demonstrate the applicability of CRDL to more complex circuit components, CRDL has been shown to have a strong advantage in power consumption over the conventional circuit techniques.
최근의 반도체 시스템에서 에너지 효율성의 문제는 점차 그 중요성을 더해가고 있다. 본 논문에서는 이러한 요구 조건을 만족시킬 수 있는 새로운 회로 기술의 하나인 전하 재활용 차동 회로 (Charge Recycling Differential Logic)에 관해 연구하였다. 이 회로는, 전하 재활용 기술을 이용하여 동작 속도의 감소없이, 기존의 회로보다 에너지 효율을 향상시킬 수 있다. 이러한 에너지 면에서의 장점 이외에 본 회로 기술은, 정적 동작으로 인한 noise margin의 향상 및 di/dt잡음의 감소 등, 집적 회로 구현에 중요한 몇 가지의 장점을 추가적으로 가진다.
본 논문은 또한 위의 호로 기술을 이용한 동기(synchronous) 및 비동기(asynchronous)파이프라인 구조(pijpeline configuration)에 관하여 다루고 있다. 먼저, CRDL은 기존의 true single-phase clock latch(TSPC)의 noise margin을 향상시킬 수 있으며, 여기서 제안된 두 개의 새로운 latch는 기존의 transmission gate latch보다 향상된 성능을 보인다. 이들 latch들과 결합된 CRDL회로는 단상(SINGLE-PHASE)의 클럭 신호(clock signal)에 의한 동작이 가능하며, 이 경우 신뢰성있는 동작을 보장하기 위한 상호 신호들 간의 시차 조건(timing condition)에 대한 분석이 행하여졌다. 한편, CRDL을 이용하여 구현된 비동기 회로는, 각 블록(block)의 동작이 완료되었음을 나타내는 감지기(completion detector)를 필요로 하지 않는 장점을 가진다. 여기서,latch 단으로 쓰이는 Muller C-element의 구조는 다소 달라졌는데, 이는 전압swing이 감소하였을때에도 회로 지연시간에 무관한 동작(delay-insensitive operation)을 보장하기 위한 것이다.
제안된 회로의 성능을 확인하기 위하여, Manchester carry chain 및 덧셈기에 대한 제작 측정 및 모사 실험이 행해졌으며, 54%~20%의 전력,지연곱의 향상을 보였다. 또한, 32-bit덧셈기 및 16-bit Booth곱셈기를 각각 동기 및 비동기 시스템의 예로 설계하였으며, 이들에 대한 모사 실험 결과는 CRDL회로가 저 전력 시스템을 설계하는데 효율적으로 이용될 수 있음을 잘 타나내고 있다.
