B-ISDN has a wide variety of services (such as voice, video, and data) which have their own quality of service (QoS) and ATM (Asynchronous Transfer Mode) switches should provide the high-speed QoS guarantee mechanism in the switch level. Input buffered ATM switches are fit for large-scale high-speed ATM switches and the bandwidth guarantee of virtual paths (VPs) is the efficient means to guarantee the QoS of each virtual channel in a switch. So, there have been a large amount of research about the bandwidth guarantee of VPs in input buffered ATM switches.
In our thesis, we propose a high-speed bandwidth guarantee mechanism, called $MC^2TSR$ (Mask Chain Cyclic Time Slot Reservation), based on the original TSR which is a high-speed throughput maximization algorithm for input buffered ATM switches. For the bandwidth guarantee, $MC^2TSR$ masks out guaranteed VPs from the reservation for the bandwidth guarantee of others. $MC^2TSR$ can allocate a large amount of bandwidth to best-effort traffics by a simple mask chain which carries bandwidth guarantee information to each input port. Fairness, all of input ports have the equal cell delay and throughput, is achieved by Cyclic Reservation Interval Function which gives the equal reservation priority to each input port.
To evaluate the performance of $MC^2TSR$, we compared TSR with $MC^2TSR$ on the bandwidth guarantee, throughputs of best-effort traffics, and cell delays of each input port by simulations. As a result, we showed that $MC^2TSR$ can guarantee the bandwidth of each VP and can allocate a large amount of bandwidth for best-effort traffics. We also showed that all of input ports have the equal delay and throughput in $MC^2TSR$.
