In the design of modern digital system, we can divide design stage into three major tasks: modeling, synthesis and optimization, validation. Today, most modeling is done in HDL (Hardware description language), and automatically synthesized. So RT-level synthesis tool is one of the most important tools.
Due to the lack of RT-level optimization, most RT-level synthesis tools miss a chance of generating better results. In this thesis, an optimization scheme is presented that is performed at RT-level synthesis.
Also a new method has been proposed for selecting storage elements based on BDD. This method is very powerful, and has been shown to be the most efficient one in selecting proper storage elements.
