In this paper, a novel vertical polycrystalline silicon(poly-Si) FET is proposed. Here, the channel length is determined by the thickness of active layer, so that the submicron FET can be made without submicron lithographic equipment. The structure is expected to be suitable for the fast circuit devices when the poly-Si film has the vertical grain structure. This is because carriers flow in the vertical direction where there are less grain boundarier than in lateral direction.
The most troublesome problem in the proposed device was such a large stand-by current that even on-current can be covered. This stand-by current is found to be due to the punch-through. We solved this problem by modifying the device structure(surround gated vertical submicron FET). Of corse, the channel doping is also effective, but surround gated FET has low stand-by current without significant threshold voltage shift.
In this paper, the proposed device is characterized. The improvement in mobility is not seen evidently, but if the modified structure(surround gated vertical FET) is adapted, the expected characteristics can be obtained, which presented in varies experimental results.