As the design complexity increases along with the improvement of semiconductor integration technology, an efficient design flow and verification strategy is crucial to the success of the design project. A new quantitative design flow and verification methodology based on profile and chronology for K486 microprocessors is suggested in this thesis.
In microprocessor design, most of time is consumed in the verification efforts to validate the design. The behavioral and structural design are verified using the high level language, C to speed up the simulation time, while the gate-level design is verified using hardware description language Verilog-XL. The consistency between each models is confirmed with the help of IPC(InterProcess Communication) and piggybacking method. The signal flow graph is used for the justification of signal integrity and the correct translation of C level model into hardware level model. For the complete software compatibility with i486, real application programs are used in board-level simulation. To increase the confidence level of test, verification coverage concept and bug life time model are introduced.
Using these quantitative verification concept, we can design and verify the CISC microprocessor successfully in a rather shorter design time compared with conventional design flow.
