In digital communication system, clock recovery is important for accurate data recovery. For this purpose, PLL is widely used. In this application, the most important thing is low noise and fast locking. However these two goals can not be achieved simultaneously with conventional method. Therefore optimum gear-shifting algorithm is proposed. In this thesis, a PLL system for HDD clock recovery with low noise and fast locking is designed and implemented using this algorithm. A simulation result shows that PLL system operating with optimum gear-shifting loop gain sequence has much better performance than others.
